A sub-0.25pJ/bit 47.6-to-58.8Gb/s reference-less FD-less single-loop PAM-4 bang-bang CDR with a deliberate-current-mismatch frequency acquisition technique in 28nm CMOS
Date of Publication:2023-07-16Hits:
- Journal:IEEE Journal of Solid-State Circuits
- Key Words:BBCDR, charge pump, CMOS,, four-level pulse-amplitude modulation (PAM), frequency detector (FD)
- Abstract:This article reports a half-rate single-loop bang bang clock and data recovery (BBCDR) circuit without the need of reference and frequency detector (FD). Specifically, we propose a deliberate-current-mismatch charge-pump pair to enable fast and robust frequency acquisition without identifying the frequency error polarity. This technique eliminates the need for a complex high-speed data or clock path during the frequency acquisition, resulting in significant power savings. Prototyped in 28-nm CMOS, the BBCDR circuit automatically tracks a four-level pulse-amplitude modulation (PAM-4) input...
- Note:■ 集成电路顶级期刊；■ 受邀发表
- Indexed by:Journal paper
- Discipline:Engineering
- First-Level Discipline:Electronics Science and Technology
- Volume:57
- Issue:5
- Page Number:1358-1371
- ISSN No.:0018-9200
- Translation or Not:no
- Date of Publication:2022-07-16
